Are you passionate about building world-class silicon?

Multiply and VisFlow are looking for an experienced ASIC/SoC Design Engineer to lead complex chip programs — from architecture and RTL through tape-out and bring-up. If you thrive on technical challenges, system-level thinking, and collaboration, this role is for you.

What You’ll Do

• Own end-to-end ASIC/SoC development — specification, RTL, verification, synthesis, and bring-up.

• Define and deliver system and chip architectures for advanced embedded, AI, and networking products.

• Lead and mentor engineers across design, verification, and physical design teams.

• Drive PPA optimization and ensure design quality from spec to silicon.

Technical Expertise

• RTL & Microarchitecture: Verilog/SystemVerilog, clocking, resets, FSMs, pipelining.

• Verification: SystemVerilog, UVM, simulators (VCS, Questa, ModelSim).

• Synthesis & Timing: Design Compiler / Genus, PrimeTime, SDC, timing closure.

• Architecture: AXI, PCIe, Ethernet, DMA, memory hierarchies, PPA trade-offs.

• Low Power & DFT: UPF/CPF, clock gating, scan/MBIST, DVFS.

• Modeling & Automation: Python/C++/SystemC, scripting (Python, Perl, Tcl).

What We Value

• Proven project ownership — from concept to silicon.

• Strong technical leadership and mentoring experience.

• Excellent problem-solving and communication skills.

Bonus Skills

• AI/ML accelerators, networking, or video pipelines.

• Multi-die / chiplet integration, 2.5D/3D packaging.

• Security architecture, IP protection, post-silicon validation.

Additional Requirements

• Can start immediately

• Working in an onsite setting

• 8+ years of work experience with Application-Specific Integrated Circuits (ASIC)